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the aps13568 is an integrated circuit that combines an ultrasensitive, omnipolar, micropower hall-effect switch with a linear programmable current regulator providing up to 150 ma to drive high brightness leds. the omnipolar hall- effect switch provides contactless control of the regulated led current, which is set by a single reference resistor. this highly integrated solution offers high reliability and ease of design compared to a discrete solution. the hall-effect switch operates with either a north or a south magnetic pole. the switch output polarity can be set with an external pulldown on the pol input pin. this allows the user to select whether the aps13568 switch output goes low when a magnet is present or when the magnetic field is removed. chopper stabilization provides low switchpoint drift over temperature. the led is turned on when the en input goes low. this active- low input can be connected directly to the hall switch output, so , to turn the led on when the switch output goes low. this flexible solution allows the user to connect additional slave switches, led drivers, pwm, or microprocessor inputs to control when the led is on. optionally, an external capacitor can be used to adjust the fade-in/fade-out feature. on-board protection for shorts to ground and thermal overload prevents damage to the aps13568 and led string by limiting the regulated current until the short is removed and/or the chip temperature has reduced below the thermal threshold. aps13568-ds ? micropower (25 a, typical) when led is of f ? linear led drive up to 150 ma ? omnipolar hall-ef fect switch low drift over temperature solid-state reliability insensitive to physical stress ? external led-enable pin for direct on/of f control ? hall-ef fect switch output supports secondary switches and/or led drivers provides switch state for other functions selectable output polarity ? automotive-grade ruggedness and fault-tolerance k temperature range qualified per aec-q100 reverse-battery and load-dump protection short-circuit protection thermal protection ? internal protection circuits enable 40 v load dump compliance without external protection components led driver with integrated micropower hall-effect switch package: figure 1: typical application diagram aps13568 features and benefits description not to scale vin so la en hall pol r iref c fade (optional) iref fade gnd 150 ma +v c bypass r pu 600 4.7 k 0.1 f continued on the next page? 8-pin soicn with exposed thermal pad (suffx lj) applications ? automotive glove boxes and storage ? automotive vanity mirrors ? t ask lighting ? consumer electronics march 13, 2017
2 selection guide part number packing package temperature range, t a (c) APS13568KLJATR-T 3000 pieces per 13-in. reel 8-pin soicn surface mount C40 to 125 aps13568eljatr-t 3000 pieces per 13-in. reel 8-pin soicn surface mount C40 to 85 absolute maximum ratings characteristic symbol notes rating unit supply voltage [1] v in (v dd ) C18 to 30 v pin en v en C18 to 30 v pin la v la C0.3 to 30 v pin so v so C0.3 to 30 v pin iref v iref C0.3 to 6.5 v pin fade v fade C0.3 to 6.5 v pin pol v pol C0.3 to 6.5 v maximum junction temperature t j(max) 165 c storage temperature t stg C65 to 170 c 1 this rating does not apply to extremely short voltage transients such as load dump and/or esd. those events have individual ratings, specific to the respective transient voltage event. specifications rohs compliant description (continued) the device is packaged in an 8-pin soicn (lj) with an exposed pad for enhanced thermal dissipation. it is rohs-compliant, with 100% matte-tin leadframe plating. the aps13568 is available in an e temperature version (up to 85c) for industrial and consumer applications, as well as a k temperature version (up to 125c) that is qualified per aec-q100 for automotive applications. led driver with integrated micropower hall-effect switch aps13568 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
3 pinout drawing and terminal list 1 2 3 4 5 6 7 8 pa d vin en so la gnd pol iref fa de package lj, 8-pin soicn pinout drawing terminal list pin number pin name description 1 vin supply voltage 2 en active-low led drive enable input 3 so active-low hall-effect switch output 4 la led anode (+) connection 5 fade fade-in/fade-out timing control 6 iref current reference resistor connection 7 pol selects led activation polarity relative to so 8 gnd ground reference C pad exposed thermal pad (may be left floating or tied to ground) clock/logic sample & hold dynamic offset cancellation control logic current regulator slew limit te mp monitor current reference la iref en r iref fade c fade so * pol micropower control circuitry and regulator vin gnd vreg c byp r pu * so can be pulled up to vin or an external voltage source. functional block diagram led driver with integrated micropower hall-effect switch aps13568 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
4 electrical characteristics: valid at t a = C40c to 125c (range k); t a = C40c to 85c (range e); v in = 7 to 24 v (unless otherwise specif?ied) characteristic symbol test conditions min. typ. [1] max. units supply and startup v in functional operating range v in (v dd ) operating, t j < 165c 7 C 24 v v in average current i inavg led off, en = high C 25 50 a v in quiescent current i inq led off, en = high, see figure 13 C 20 45 a v in active current i in(act) i la = 0 ma, en = low, see figure 13 C 4 6 ma startup time t on measured from v in > 7 v to i la > 90% of 150 ma with pol = gnd, en = low, r iref = 600 ?, f ade disabled (see fade pin description below) C C 1 ms external response time t ext_on measured from en < v il to i la > 90% of 150 ma with v in > 7 v, r iref = 600 ?, fade disabled (see fade pin description below) C 50 C s supply zener clamp v oltage v in(z) i in(act) = 6.5 ma, t a = 25c 32 45 C v micropower operation period t period see figure 13 C 50 C ms awake time t awake C 50 C s led current regulation reference voltage v iref 267 a < i ref < 2 ma C 1.2 C v reference current ratio g h i la i ref C 75 C C current accuracy [2][3][4] e ila 4.5 k > r iref > 600 C5 C 5 % output source current i la r iref = 600 , led driver enabled (see table 1) C 150 170 ma dropout v oltage v do v in C v la , i la = 150 ma C C 2.4 v v in C v la , i la = 75 ma C 800 C mv current slew time t fade(min) current rising or falling between 10% and 90%, fade disabled (see fade pin description below) C 10 C s en and pol inputs en input logic-low voltage v il(en) C C 0.8 v en input logic-high voltage v ih(en) 2 C C v en input current i logic-in(en) C2 C 2 a pwm duty cycle [5][6] dc pwm applied to en; 0 v v pwm 5.25 v 0 C 100 % pwm frequency range [5] f pwm pwm applied to en; 0 v v pwm 5.25 v 0 C 1 khz pwm input v oltage v pwm pwm applied to en 0 C 5.25 v pol input logic-low voltage v il(pol) C C 0.8 v pol average leakage current i logic-in(pol) pol = gnd C 80 C na continued on next page... led driver with integrated micropower hall-effect switch aps13568 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
5 characteristic symbol test conditions min. typ. [1] max. units logic outputs output on voltage v out(sat) so, i out = 20 ma, b > b op , pol = float C 180 500 mv output current limit i output(sink)c so, t j < t j(max) 30 C 60 ma output rise time t r so, r l = 820 , c s = 20 pf C 0.2 C s output fall time t f so, r l = 820 , c s = 20 pf C 0.1 C s power-on state pos so , pol = gnd or pol = float high C analog inputs input voltage range v input iref, fade 0 C 5.5 v protection short detect voltage v scd measured at la 1.2 C 1.8 v short circuit source current i scs short present la to gnd C 1 C ma short release voltage hysteresis v schys C 350 C mv thermal monitor activation temperature t jm C 130 C c thermal monitor slope i sen /t j C C3.25 C %/c thermal monitor low current temperature t jl C 150 C c overtemperature shutdown t jf temperature increasing C 170 C c overtemperature hysteresis t jhys C 15 C c magnetic characteristics [7] operate point b ops |b field | > |b op | C 40 70 g b opn C70 C40 C g release point b rps |b field | < |b rp | 5 25 C g b rpn C C25 C5 g hysteresis b hys |b opx C b rpx | 5 15 25 g 1 typical data is at t a = 25c and v in = 12 v . 2 resistor tolerance is not included. 3 when en = low, e ila = 100 [( | i la | r iref / 90 ) C 1], with i la in ma and r iref in k. 4 current accuracy cannot be guaranteed once the device is in thermal monitor actuation protection. 5 guaranteed by design, not tested in production. 6 at high pwm input frequencies, the current slew time may not provide sufficient time for i la to reach either the user-selected maximum current or minimum current as the duty cycle approaches 0% and/or 100%. see dimming frequency and duty cycle section. 7 magnetic flux density, b, is indicated as a negative value for north-polarity magnetic fields, and is a positive value for south-polarity magnetic fields. electrical characteristics (continued): valid at t a = C40c to 125c (range k); t a = C40c to 85c (range e); v in wr 9xqohvvrwkhulvhvshflilhg led driver with integrated micropower hall-effect switch aps13568 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
6 thermal characteristics characteristic symbol test conditions value units thermal resistance (junction to ambient) r ja (high-k) jedec package ms-012 ba. test is performed using a high thermal conductivity, multilayer printed circuit board that approximates those specified in the jedec standards jesd51-7. thermal vias are included per jesd51-5. see figure 2 for more detail. 35 c/w r ja (usual-k) jedec package ms-012 ba. multiple measurement points on both single- and dual-layer printed circuit boards with minimal exposed copper (2-oz) area. see figure 2 for more detail. 62-147 c/w 200 150 100 50 0 0.2 0.4 0.6 0.8 area of copper, one side (in ) 2 package thermal resistance (oc/w) one-sided board two-sided board figure 2: thermal resistance (r ja ) versus copper area on printed circuit board (pcb) ? all copper is 2 oz. thickness ? area of copper refers to individual test locations on pcb led driver with integrated micropower hall-effect switch aps13568 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
7 characteristic performance 0 1 2 3 4 5 6 -50 0 50 100 150 v in current, i in (ma) ambient temperature, t a ( c) v in active current (i in(act) v. t a ) 7 v 12 v 18 v 24 v 0 1 2 3 4 5 6 0 5 10 15 20 25 30 v in current, i in (ma) supply voltage, v in (v) v in active current (i in(act) v. v in ) -40c 25c 125c 0 5 10 15 20 25 30 35 40 45 50 -50 0 50 100 150 v in current, i in (a) ambient temperature, t a ( c) v in average current (i inavg v. t a ) 7 v 12 v 18 v 24 v 0 5 10 15 20 25 30 35 40 45 50 0 5 10 15 20 25 30 v in current, i in (a) supply voltage, v in (v) v in average current (i inavg v. v in ) -40c 25c 125c 0 50 100 150 200 250 300 350 400 450 500 -50 0 50 100 150 output on voltage, v out(sat) (mv) ambient temperature, t a ( c) output on voltage (v out(sat) v. t a ) 7 v 12 v 18 v 24 v 0 50 100 150 200 250 300 350 400 450 500 0 5 10 15 20 25 30 output on voltage, v out(sat) (mv) supply voltage, v in (v) output on voltage (v out(sat) v. v in ) -40c 25c 125c 0 5 10 15 20 25 30 35 40 45 50 -50 0 50 100 150 v in current, i in (a) ambient temperature, t a ( c) v in average current (i inavg v. t a ) 7 v 12 v 18 v 24 v 0 5 10 15 20 25 30 35 40 45 50 0 5 10 15 20 25 30 v in current, i in (a) supply voltage, v in (v) v in average current (i inavg v. v in ) -40c 25c 125c led driver with integrated micropower hall-effect switch aps13568 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
8 0 5 10 15 20 25 30 35 40 45 -50 0 50 100 150 v in current, i in (a) ambient temperature, t a ( c) v in quiescent current (i inq v. t a ) 7 v 12 v 18 v 24 v 0 5 10 15 20 25 30 35 40 45 0 5 10 15 20 25 30 v in current, i in (a) supply voltage, v in (v) v in quiescent current (i inq v. v in ) -40c 25c 125c 1 1.05 1.1 1.15 1.2 1.25 1.3 1.35 1.4 -50 0 50 100 150 reference voltage, v iref (v) ambient temperature, t a ( c) reference voltage (v iref v. t a ) 7 v 12 v 18 v 24 v 1 1.05 1.1 1.15 1.2 1.25 1.3 1.35 1.4 0 5 10 15 20 25 30 reference voltage, v iref (v) supply voltage, v in (v) reference voltage (v iref v. v in ) -40c 25c 125c 17 18 19 20 21 22 23 -50 0 50 100 150 output source current, i la (ma) ambient temperature, t a ( c) output source current (i la v. t a ) i ref = 0.267 ma 7 v 12 v 18 v 24 v 17 18 19 20 21 22 23 0 5 10 15 20 25 30 output source current, i la (ma) supply voltage, v in (v) output source current (i la v. v in ) i ref = 0.267 ma -40c 25c 125c for output source current and reference current ratio, the thermal monitor activation is disabled during test. 0 5 10 15 20 25 30 35 40 45 -50 0 50 100 150 v in current, i in (a) ambient temperature, t a ( c) v in quiescent current (i inq v. t a ) 7 v 12 v 18 v 24 v 0 5 10 15 20 25 30 35 40 45 0 5 10 15 20 25 30 v in current, i in (a) supply voltage, v in (v) v in quiescent current (i inq v. v in ) -40c 25c 125c led driver with integrated micropower hall-effect switch aps13568 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
9 70 72 74 76 78 80 -50 0 50 100 150 output source current, i la (ma) ambient temperature, t a ( c) output source current (i la v. t a ) i ref = 1.0 ma 7 v 12 v 18 v 24 v 70 72 74 76 78 80 0 5 10 15 20 25 30 output source current, i la (ma) supply voltage, v in (v) output source current (i la v. v in ) i ref = 1.0 ma -40c 25c 125c 145 147 149 151 153 155 -50 0 50 100 150 output source current, i la (ma) ambient temperature, t a ( c) output source current (i la v. t a ) i ref = 2.0 ma 7 v 12 v 18 v 24 v 145 147 149 151 153 155 0 5 10 15 20 25 30 output source current, i la (ma) supply voltage, v in (v) output source current (i la v. v in ) i ref = 2.0 ma -40c 25c 125c 65 67 69 71 73 75 77 79 81 83 85 -50 0 50 100 150 reference current ratio, g h ambient temperature, t a ( c) reference current ratio (g h v. t a ) i ref = 0.267 ma 7 v 12 v 18 v 24 v 65 67 69 71 73 75 77 79 81 83 85 0 5 10 15 20 25 30 reference current ratio, g h supply voltage, v in (v) reference current ratio (g h v. v in ) i ref = 0.267 ma -40c 25c 125c for output source current and reference current ratio, the thermal monitor activation is disabled during test. led driver with integrated micropower hall-effect switch aps13568 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
10 0 1 2 3 4 5 -50 0 50 100 150 dropout voltage, v do (v ambient temperature, t a ( c) dropout voltage (v do v. t a ) v in = 7 v 20 ma 50 ma 100 ma 150 ma 0 1 2 3 4 5 0 20 40 60 80 100 120 140 160 dropout voltage, v do (v) output source current, i la (ma) dropout voltage (v do v. i la ) v in = 7 v -40c 25c 125c 0 10 20 30 40 50 60 70 -50 0 50 100 150 operate point, b ops (g) ambient temperature, t a ( c) operate point, south (b ops v. t a ) 7 v 12 v 18 v 24 v 0 10 20 30 40 50 60 70 0 5 10 15 20 25 30 operate point, b ops (g) supply voltage, v in (v) operate point, south (b ops v. v in ) -40c 25c 125c 0 10 20 30 40 50 60 70 -50 0 50 100 150 release point, b rps (g) ambient temperature, t a ( c) release point, south (b rps v. t a ) 7 v 12 v 18 v 24 v 0 10 20 30 40 50 60 70 0 5 10 15 20 25 30 release point, b rps (g) supply voltage, v in (v) release point, south (b rps v. v in ) -40c 25c 125c led driver with integrated micropower hall-effect switch aps13568 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
11 -70 -60 -50 -40 -30 -20 -10 0 -50 0 50 100 150 operate point, b opn (g) ambient temperature, t a ( c) operate point, north (b opn v. t a ) 7 v 12 v 18 v 24 v -70 -60 -50 -40 -30 -20 -10 0 0 5 10 15 20 25 30 operate point, b opn (g) supply voltage, v in (v) operate point, north (b opn v. v in ) -40c 25c 125c -70 -60 -50 -40 -30 -20 -10 0 -50 0 50 100 150 release point, b rpn (g) ambient temperature, t a ( c) release point, north (b rpn v. t a ) 7 v 12 v 18 v 24 v -70 -60 -50 -40 -30 -20 -10 0 0 5 10 15 20 25 30 release point, b rpn (g) supply voltage, v in (v) release point, north (b rpn v. v in ) -40c 25c 125c 5 7 9 11 13 15 17 19 21 23 25 -50 0 50 100 150 hysteresis, b hys (g) ambient temperature, t a ( c) hysteresis (b hys v. t a ) 7 v 12 v 18 v 24 v 5 7 9 11 13 15 17 19 21 23 25 0 5 10 15 20 25 30 hysteresis, b hys (g) supply voltage, v in (v) hysteresis (b hys v. v in ) -40c 25c 125c led driver with integrated micropower hall-effect switch aps13568 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
12 functional description overview the aps13568 is an integrated hall-effect switch with a linear current regulator which is designed to provide drive current and protection for a string of series connected high-brightness leds in automotive applications. it provides a single programmable current output sourcing up to 150 ma, with low dropout voltage. the aps13568 is designed for illumination applications where the led activity is controlled by the integrated hall-effect switch, external logic, or by a pwm input signal such as from an mcu (microcontroller). current regulation is maintained and the leds are protected during a short to ground at any point in the led string. a short to ground on the output terminal will disable the output until the short is removed. integrated thermal management reduces the regulated current level at high internal junction temperatures to limit power dissipation. omnipolar operation the integrated hall-effect switch in the aps13568 is an omnipo- lar switch. the output switches when a magnetic field perpendic- ular to the hall sensor exceeds the operate point threshold, b opx (b > b ops or b < b opn ). when magnetic field is reduced below the release point, b rpx (b < b rps or b > b rpn ), the device output goes to the other state. the output transistor is capable of sinking current up to the short-circuit current limit, i om , which ranges from 30 to 60 ma. the difference in the magnetic operate and release points is the hysteresis, b hys , of the device. this built-in hysteresis allows clean switching of the output even in the pres- ence of external mechanical vibration and electrical noise. removal of the magnetic field results in an output state consis- tent with b < b rpx . since the output state polarity relative to the magnetic thresholds is user-selectable via the pol pin, reference table 1 to determine the expected output state. b rpn b opn b rps b ops b hys b hys 0 g sw_out decreasing north field increasing south field decreasing south field increasing north field active low pulled high increasing south field increasing north field figure 3: hall switch output (so) state versus magnetic field (pol = float) figure 4: hall switch output (so) state versus magnetic field (pol = gnd) b rpn b opn b rps b ops b hys b hys 0 g sw_out decreasing north field increasing south field decreasing south field increasing north field active low pulled high increasing south field increasing north field led driver with integrated micropower hall-effect switch aps13568 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
13 pin functions vin supply to the micro-power control circuit and current regulator. a ceramic bypass capacitor, typically 100 nf, should be connected as close as possible to this pin and gnd. see figure 1 typical application circuit. so active-low open-drain output of the hall-effect switch (requires pull-up resistor, r pu ). the output polarity of so depends on the configuration of the pol pin. see figure 3 and figure 4 and table 1. drives low when b field > |b op | when pol = float, or pulled high through a pull-up resistor on so when pol = gnd. pol inverts so polarity, as shown in table 1. see figure 3 and figure 4. table 1: so state truth table (pol) pol b field so state gnd |b| > |b op | high |b| < |b rp | low float |b| > |b op | low |b| < |b rp | high pol should only be tied to ground or floated to achieve the desired output polarity. the led driver is only enabled when the en pin is pulled low. if so is tied to en, changing the so polar- ity changes the behavior between led off (pol = gnd) and led on (pol = float) with a magnet present. en active-low logic input to enable/disable the led driver. table 2: led driver state truth table (en) en state led driver state low led driver enabled; device is in active mode high led driver disabled; device operates in micropower mode this provides direct on/off action and can be used for pwm con- trol when the fade function is disabled. see fade pin description below. tie to so for standalone aps13568 operation. fade a capacitor between this pin and gnd controls the turn-on and turn-off times of the led current. to disable the fade feature, omit c fade and float the fade pin. iref a 1.2 v reference used to set the led current drive. connect resis- tor r iref to gnd to set the reference current. see equation 1. la current source output connected to the anode of the first led in the string. gnd ground reference connection. this pin should be connected directly to the negative supply. led driver with integrated micropower hall-effect switch aps13568 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
14 pad isolated pad for thermal dissipation only. it may be left floating, but it is recommended to connect this pad to ground. figure 5: power-on timing t t v v in(min ) t on 0 output state undefined for v in < v in(min) pos v out(sat ) v out(high) v so v in key pos b < b rp (pol = gnd) b > b op (pol = float) b > b op (pol = gnd) b < b rp (pol = float) b rp < b < b op power-on behavior device power-on occurs once t on has elapsed. during the time prior to t on , and after v in > v in(min) , the output state is high, regardless of the pol configuration. after t on has elapsed, the output will correspond with the applied magnetic field for b > b op or b < b rp . see figure 5 for an example. powering-on the device in the hysteresis range (less than b opx and greater than b rpx ) causes the output state to be high. the correct state is attained after the first excursion beyond b opx or b rpx . led current level the led current is controlled by a linear current regulator between the vin pin and the la output. the basic equation that determines the nominal output current at this pin is: given that the led driver is enabled (see table 1), i= la v ref g h r iref (1 ) where i la is in a and r iref is in ; v ref g h is 90. note: the output current may be reduced from the set level by the thermal monitor circuit. conversely, the reference resistor may be calculated from: r = iref i la (2 ) v ref g h where i la is in a, r iref is in , v ref = 1.2 v , and g h = 75. for example, where the required current is 75 ma, the resistor value will be: r = iref 1.2 v 75 0.075 a (3) = 1.2 k it is important to note that because the aps13568 is a linear current regulator, the maximum regulated current is limited by the power dissipation and thermal management in the application. all current calculations assume an adequate heat sink and/or airflow for the power dissipated. the application section below provides further detail on thermal management and the associated limitations. fade-in/fade-out fade timing is controlled by external capacitor, c fade , on the fade pin. a larger capacitor will result in a longer fade time. the 10%-90% fade time is approximated by the equation: t fade = c fade 0.8 10 6 (4 where t fade is in seconds and c fade is in farads. fade-in is triggered when the led driver is enabled and fade-out is triggered when the led driver is disabled (see table 1). to disable the fade feature, omit c fade and float the fade pin. led driver with integrated micropower hall-effect switch aps13568 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
15 vin la gnd aps13568 shorted output is disabled. low current is sourced to detect when short is cleared. figure 7: output short to ground vin la gnd aps13568 only shorted led(s) is(are) inactive. current remains regulated in non-shorted led(s). figure 8: shorted led(s) vin la gnd aps13568 any led cathode short to ground. current remains regulated in non-shorted leds. figure 6: any cathode short to ground led driver with integrated micropower hall-effect switch aps13568 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
16 dimming frequency and duty cycle dimming of the led can be controlled by applying a pulse- width-modulated (pwm) signal to the en pin (see table 2). the duty cycle of the pwm directly correlates to the duty cycle of the led current, provided that the fade function is disabled (see fade pin description above). this controls the relative led on-time versus off-time and changes the perceived brightness of the led. the en pin is rated for the full range of v in and therefore when tied directly to the so pin, v in can be used as the pull-up supply for so. when using the pwm capabilities, the pwm input voltage (v pwm ) applied to the en pin should be in the range of 0 to 5.25 v. the en input has typical ttl switching thresholds, but exceeding 5.25 v may cause pulse-width (duty-cycle) distortion. the pwm input frequency (f pwm ) can be as high as 1 khz. the combination of the external response time (t ext_on ) and i la current slew time (t fade ) may not provide sufficient time for the desired/user-set la on and off current levels to be reached when en is pulsed with short on/off times. see figure 9 and figure 10. this only affects the proportionality between the input pwm duty cycle on en and la duty cycle (and therefore average la current) at higher pwm carrier frequencies in conjunction with very low or very high duty cycle (see figure 11). figure 11 shows that with 100 hz pwm frequency, all duty cycles from 0% to 100% are capable of producing an output current equal to the user-set i la level. however, at 1 khz pwm frequency, duty cycles from 95% to 100% produce an output which does not reach the user-set i la current. the users pwm algorithm can adjust the duty cycle range accordingly. for example, with a pwm frequency of 1 khz and duty cycle of 1% or 99%, the en on time is 1% 1 khz = 10 s. the exter - nal response time (t ext_on ) and i la current slew time (t fade ) is 50 s (typ) + 10 s (typ). safety features the circuit includes several features to ensure safe operation and to protect the leds and the aps13568: ? the current regulator between vin and la output provide a natural current limit due to the regulation. ? the la output includes a short-to-ground detector that will disable the output to limit the dissipation. ? the thermal monitor reduces the regulated current as the temperature rises. ? thermal shutdown completely disables the outputs under extreme overtemperature conditions. figure 9 : low pwm duty cycle en i la t ext_on 0 ? x ? (user-set level) figure 10: high pwm duty cycle en i la 0 ? x ? (user-set level) figure 11: la duty cycle vs. en pwm duty cycle 100 0 0 100 led constant on led constant off la duty cycle (%) en pwm duty cycle (%) f pwm = 100 hz f pwm = 1000 hz led driver with integrated micropower hall-effect switch aps13568 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
17 short-circuit detection a short to ground on an led cathode as in figure 6 will not result in a short-to-ground fault condition. the current through the remaining leds will remain in regulation and the leds will be protected. if the la output is pulled below the short detect voltage as in figure 7, it will disable the driver output. a small current will be sourced from the disabled output to monitor the short and detect when it is removed. when the voltage at la rises above the short detect voltage, the driver will be re-enabled. a shorted led or leds in a multi-led string, as in figure 8, will not result in a short fault condition. the current through the remaining leds will remain in regulation and the leds will be protected. thermal protection will still operate normally in all described led short-circuit conditions. short-circuit detection is shut off to minimize power consumption when the led driver is disabled. temperature monitor and thermal protection the temperature monitor function included in the aps13568 reduces the led current as the silicon junction temperature increases (see figure 12). as the junction temperature of the aps13568 increases, the regulated current level is reduced, reducing the dissipated power in the aps13568 and in the leds. the current is reduced from the 100% level at typically 3.25%/c until the point at which the current drops to 25% of the full value, defined at t jl . above this temperature, the current will continue to reduce at a lower rate until the temperature reaches the over- temperature shutdown threshold temperature, t jf . if the chip temperature exceeds the overtemperature limit t jf , the driver will be disabled. the temperature will continue to be moni- tored and the regulator will be re-activated when the temperature drops below the threshold provided by the specified hysteresis. note that it is possible for the aps13568 to transition rapidly between thermal shutdown and normal operation. this can hap- pen if the thermal mass attached to the exposed thermal pad is small and t jm is increased to close to the shutdown temperature. the period of oscillation will depend on t jm , the dissipated power, the thermal mass of any heatsink present, and the ambient temperature. by mounting the aps13568 in close proximity and on the same thermal substrate as the leds, this feature can also be used to limit the dissipation of the leds. micropower operation the built-in micropower control periodically activates the hall switch circuitry for a short period of time (t awake ), and deacti - vates it for the remainder of the period (t period ). the short dura - tion awake state allows for sensor stabilization prior to sampling the hall switch and latching the state on the so output. if the so output state is off (high), it is kept high during the sleep period; updates to the output from the off-state only occur at the end of the active (t awake ) pulse. if the output state is on (low), the hall switch circuitry will remain awake until the output switches back off. the ics supply current is not affected by the output state, provided the led driver is disabled. the micropower control operates independently of the led driver state. if en is forced low by an external circuit, the device will also remain in the awake mode. at power-on, the aps13568 will sample a t awake cycle before the first t sleep cycle. figure 13: micropower timing diagram i in(act) i inq sample and output latched t awake t period sleep 100 90 80 60 40 20 25 0 70 90 11 0 130 150 170 t jm t jf t jl junction te mperature, t (oc) j relative sense current (%) figure 12: temperature monitor current reduction led driver with integrated micropower hall-effect switch aps13568 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
18 application information power dissipation the most critical design consideration when using a linear regula - tor such as the aps13568 is the power produced internally as heat and the rate at which that heat can be dissipated. there are three sources of power dissipation in the aps13568: ? the quiescent power to run the control circuits ? the power in the reference circuit ? the power due to the regulator voltage drop quiescent power the quiescent power is the product of the quiescent current (i inq ) and the supply voltage (v in ), and it is not related to the regulated current. the quiescent power (p q ) is therefore defined as: p q = v in i inq (5) reference power the reference circuit draws the reference current from the supply and passes it through the reference resistor to ground. the refer- ence circuit power is the product of the reference current and the difference between the supply voltage and the reference voltage, typically 1.2 v . the reference power (p ref ) is therefore defined as: p ref = (v ?v v in re fr ef ) r iref (6) regulator power in most application circuits, the largest dissipation will be pro- duced by the output current regulator. the power dissipated the current regulator is simply the product of the output current and the voltage drop across the regulator. the regulator power the output is defined as: p reg = (v in C v led ) i led (7) note that the voltage drop across the regulator (v reg ) is always greater than the specified minimum dropout voltage (v do ). the output current is regulated by making this voltage large enough to provide the voltage drop from the supply voltage to the total forward voltage of all leds in series (v led ). the total power dissipated in the aps13568 is the sum of the quiescent power, the reference power, and the power in the regulator: p d = p q + p reg C p ref (8) the power that is dissipated in the leds is: p led = v led i led (9) where v led is the voltage across all leds in the string. from these equations (and as illustrated in figure 12), it can be seen that, if the power in the aps13568 is not limited, then it will increase as the supply voltage increases while the power in the leds will remain constant. dissipation limits the thermal shutdown feature limits the power that can be dis- sipated by the aps13568. thermal shutdown if the thermal resistance from the aps13568 to the ambient environment is high, then the silicon temperature will rise to the thermal shutdown threshold and the led current will be disabled. after the current is disabled the power dissipated will drop and the temperature will fall. when the temperature falls by the hysteresis of the thermal shutdown circuit, the driver will be re-enabled and the temperature will start to rise again. this cycle will repeat continuously until the ambient temperature drops or the aps13568 is switched off. the period of this thermal shut- down cycle will depend on several electrical, mechanical, and thermal parameters. supply voltage limits in many applications, especially in automotive systems, the avail- able supply voltage can vary over a two-to-one range, or greater when double battery or load dump conditions are taken into con- sideration. in such systems, is it necessary to design the applica- tion circuit such that the system meets the required performance targets over a specified voltage range. to determine this range when using the aps13568, there are two limiting conditions: ? for maximum supply voltage, the limiting factor is the power that can be dissipated from the regulator without exceeding the led driver with integrated micropower hall-effect switch aps13568 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
19 temperature at which the thermal foldback starts to reduce the output current below an acceptable level. ? for minimum supply voltage, the limiting factor is the maximum dropout voltage of the regulator , where the difference between the load voltage and the supply is insufficient for the regulator to maintain control over the output current. minimum supply limit: regulator saturation voltage the supply voltage (v in ) is always the sum of the voltage drop across the high-side regulator (v reg ) and the forward voltage of the leds in the string (v led ). v led is constant for a given current and does not vary with sup- ply voltage. therefore, v reg provides the variable difference between v led and v in . v reg has a minimum value below which the regulator can no longer be guaranteed to maintain the output current within the specified accuracy. this level is defined as the regulator dropout voltage (v do ). the minimum supply voltage, below which the led current does not meet the specified accuracy, is therefore determined by the sum of the minimum dropout voltage (v do ) and the forward volt - age of the leds in the string (v led ). the supply voltage must always be greater than this value and the minimum specified supply voltage, that is: v in > v do + v led and v in > v in(min) (10) as an example, consider a string of two white leds, running at 150 ma, with each led forward voltage at 3.15 v . the minimum supply voltage will be approximately: v in(min) = 0.8 + (2 3.15) = 7.1 v (1 1) maximum supply limit: thermal limitation as described above, when the silicon temperature reaches the thermal shutdown threshold the thermal protection feature causes the output current to be disabled. the maximum supply voltage is therefore defined as the voltage above which the led current drops below the acceptable minimum. this can be estimated by determining the maximum power that can be dissipated before the internal (junction) temperature of the aps13568 reaches the thermal shutdown threshold. the maximum power dissipation is defined as: p d(max) = r ja t (max) (12) where t (max) is the difference between the thermal protection activation temperature of the aps13568 and the maximum ambi- ent temperature t a (max), and r ja is the thermal resistance from the internal junctions in the silicon to the ambient environment. thermal dissipation the amount of heat that can pass from the silicon of the aps13568 to the surrounding ambient environment depends on the thermal resistance of the structures connected to the aps13568. the thermal resistance (r ja ) is a measure of the temperature rise created by power dissipation and is usually mea- sured in degrees celsius per watt (c/w). the temperature rise (t) is calculated from the power dissipated (p d ) and the thermal resistance (r ja ) as: t = p d r ja (13) a thermal resistance from silicon to ambient (r ja ) of approxi- mately 35c/w can be achieved by using a high thermal conduc- tivity, multilayer printed circuit board as specified in the jedec standards jesd51-7 for jedec package ms-012 ba (including thermal vias as called out in jesd51-5). additional improve - ments may be achieved by optimizing the pcb design. optimizing thermal layout the features of the printed circuit board, including heat conduc- tion and adjacent thermal sources such as other components, have a significant effect on the thermal performance of the device. to optimize thermal performance, the following should be taken into account: ? maximizing the forward voltage of the leds relative to the v in of the aps13568 will greatly reduce the power dissipated in the aps13568 by reducing the voltage drop across the aps13568. ? the aps13568 exposed thermal pad should be connected to as much copper area as is available. this copper area may be left floating or connected to ground if desired. ? copper thickness should be as high as possible (for example, 2 oz. or greater for higher power applications). ? the greater the quantity of thermal vias, the better the led driver with integrated micropower hall-effect switch aps13568 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
20 dissipation. if the expense of vias is a concern, studies have shown that concentrating the vias directly under the device in a tight pattern, as shown in figure 14, has the greatest effect. ? additional exposed copper area on the opposite side of the board should be connected by means of thermal vias. the copper should cover as much area as possible. ? other thermal sources should be placed as far away from the device as possible. extensive applications information for hall ef fect devices is available in: ? hall-effect ic applications guide (an27701) ? soldering methods for allegros products smd and through-hole (an26009) ? guidelines for designing subassemblies using hall-effect devices (an27703.1) ? handling, storage and shelf life of semiconductor devices (an296126) ? chemical exposur e of devices (an295047) signal traces lj package exposed thermal pad top layer exposed copper ? 0.3 mm vi a lj package outline 0.7 mm 0.7 mm figure 14: suggested pcb layout for thermal optimization (maximum available bottom-layer copper recommended) ? allegr o hall-effect sensor ics (an296065) ? integrating hall-effect magnetic sensing technology into modern household appliances (an295046) ? omnipolar switch hall-effect ic basics (an296070) all are provided on the allegro website, www.allegromicro.com. led driver with integrated micropower hall-effect switch aps13568 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
21 package outline drawing for reference only ?n ot for tooling use (reference ms-012ba) dimensions in millimeters ? not to scale dimensions exclusive of mold ?ash, gate burrs, and dambar protrusions exact case and lead con?guration at supplier discretion within limits shown 3.30 2 1 8 c 1.27 5.60 2.41 1.75 0.65 2.41 nom 3.30 nom c 1.27 bsc b d 2 1 8 c seating plane c 0.10 8x 0.25 bsc 1.04 ref 1.70 max 4.90 0.10 3.90 0.10 6.00 0.20 0.51 0.31 0.15 0.00 0.25 0.17 1.27 0.40 8 0 a branded face seating plane gauge plane pcb layout reference vi ew a b c d terminal #1 mark area exposed thermal pad (bottom surface) hall element (e1) centered in package (not to scale). reference land pattern layout (reference ipc7351 soic127p600x175-9am); all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and pcb layout tolerances; when mountin g on a multilayer pcb, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference eia/jedec standard jesd51-5) e1 hall element 0.115 mm left from center figure 15: package lj, 8-pin soicn with exposed thermal pad led driver with integrated micropower hall-effect switch aps13568 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
22 for the latest version of this document, visit our website: www.allegromicro.com revision history number date description C march 13, 2017 initial release copyright ?2017, allegro microsystems, llc allegro microsystems, llc reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. before placing an order, the user is cautioned to verify that the information being relied upon is current. allegros products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of allegros product can reasonably be expected to cause bodily harm. the information included herein is believed to be accurate and reliable. however, allegro microsystems, llc assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. led driver with integrated micropower hall-effect switch aps13568 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com

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